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VASY(1)			   CAO-VLSI Reference Manual		       VASY(1)

NAME
       VASY - VHDL Analyzer for	Synthesis

SYNOPSIS
       vasy [-VpavsoipSHL] [-C num] [-E	num] [-I format] [-P file] filename
       [outname]

DESCRIPTION
       VASY  is	 a  hierarchical VHDL Analyzer for Synthesis.  VASY performs a
       semantic	analysis of a VHDL RTL description filename, with a VHDL  sub-
       set  much more extended than the	Alliance one (see vasy(5) for more de-
       tails), and identifies with precision all the memorizing	 elements  and
       tristate	buffers.
       During  its analysis, VASY expands generic parameters, executes generic
       map and generate	statements, and	also unrolls static FOR	loops.
       At the end, VASY	drives an equivalent description outname  (in  Verilog
       or VHDL format) accepted	by most	of synthesis tools.

ENVIRONMENT VARIABLES
       MBK_WORK_LIB(1)
		 indicates  the	 path to the read/write	directory for the ses-
		 sion.

OPTIONS
       -V	 Verbose mode on.  Each	step of	the analysis is	 displayed  on
		 the standard output.

       -v	 Drives	an equivalent description in Verilog format.

       -a	 Drives	 an  equivalent	 description  in  Alliance VHDL	format
		 vbe(5)	and/or vst(5).	We can note that with this option, all
		 arithmetic operators are expanded in  an  equivalent  set  of
		 boolean  expressions, because these operators don't belong to
		 the Alliance VHDL subset.

       -s	 Drives	an equivalent VHDL  description	 (with	the  extention
		 .vhd) accepted	by most	of industrial synthesis	tools.

       -S	 Uses  Std_logic  instead of Bit (taken	into account only with
		 option	-s).

       -i	 Drives	initial	signal values (taken into  account  only  with
		 option	-s).

       -I format Specifies  the	VHDL input format such as Alliance VHDL	format
		 vbe(5), vst(5)	or industrial VHDL format vhd or vhdl.

       -H	 In a structural description, all model	of instances  are  re-
		 cursively  analyzed.	(By  default VASY analyzes only	models
		 with generic parameters) The leaves cells are	defined	 by  a
		 file called CATAL (see	catal(5) for details).

       -o	 Authorizes to overwrite existing files.

       -p	 Adds  power supply connectors (vdd and	vss). Useful option to
		 enter in Alliance.

       -C num	 When the size of the adder is greater or equal	to num a Carry
		 Look Ahead adder is generated,	 instead  of  a	 Ripple	 Carry
		 adder.	 (taken	into account only with option -a).

       -E num	 Comparators  are expanded in an equivalent set	of boolean ex-
		 pressions, when their size is greater than  num  (taken  into
		 account only with option -a).

       -L	 A  file .lax (see lax(5) for details) is generated. This file
		 contains the list of all signals that must be kept during the
		 synthesis step, using boom (see boom(1) for details).	(taken
		 into account only with	option -a).

       -P file	 Specifies a 'file.pkg'	containing a list of logical and phys-
		 ical package name:
		 # Example
		 work.constants.all  : pkg_constants
		 work.components.all : pkg_components

SEE ALSO
       vasy(5),	 vbe(5),  vhdl(5),  catal(5).	lax(5).	  asimut(1),  boom(1),
       MBK_WORK_LIB(1).	 MBK_CATA_LIB(1).  MBK_CATAL_NAME(1).

ASIM/LIP6		       November	26, 1999		       VASY(1)

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