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PMC.OCTEON(3) FreeBSD Library Functions Manual PMC.OCTEON(3) NAME pmc.octeon -- measurement events for Octeon family CPUs LIBRARY Performance Monitoring Counters Interface Library (libpmc, -lpmc) SYNOPSIS #include <pmc.h> DESCRIPTION There are two counters per core supported by the hardware and each is 64 bits wide. Event Specifiers (Programmable PMCs) MIPS programmable PMCs support the following events: CLK (Event 1) Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) ISSUE (Event 2) Instructions issued but not retired RET (Event 3) Instructions retired NISSUE (Event 4) Cycles no issue SISSUE (Event 5) Cycles single issue DISSUE (Event 6) Cycles dual issue IFI (Event 7) Cycle ifetch issued (but not necessarily commit to pp_mem) BR (Event 8) Branches retired BRMIS (Event 9) Branch mispredicts J (Event 10) Jumps retired JMIS (Event 11) Jumps mispredicted REPLAY (Event 12) Mem Replays IUNA (Event 13) Cycles idle due to unaligned_replays TRAP (Event 14) trap_6a signal UULOAD (Event 16) Unexpected unaligned loads (REPUN=1) UUSTORE (Event 17) Unexpected unaligned store (REPUN=1) ULOAD (Event 18) Unaligned loads (REPUN=1 or USEUN=1) USTORE (Event 19) Unaligned store (REPUN=1 or USEUN=1) EC (Event 20) Exec clocks(must set CvmCtl[DISCE] for accurate tim- ing) MC (Event 21) Mul clocks(must set CvmCtl[DISCE] for accurate timing) CC (Event 22) Crypto clocks(must set CvmCtl[DISCE] for accurate tim- ing) CSRC (Event 23) Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) CFETCH (Event 24) Icache committed fetches (demand+prefetch) CPREF (Event 25) Icache committed prefetches ICA (Event 26) Icache aliases II (Event 27) Icache invalidates IP (Event 28) Icache parity error CIMISS (Event 29) Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) WBUF (Event 32) Number of write buffer entries created WDAT (Event 33) Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) WBUFLD (Event 34) Number of write buffer entries forced out by loads WBUFFL (Event 35) Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) WBUFTR (Event 36) Number of stores that found no available write buffer entries BADD (Event 37) Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) BADDL2 (Event 38) Number of address bus cycles not reflected (i.e. des- tined for L2) (may need to set CvmCtl[DISCE] for accurate counts) BFILL (Event 39) Number of fill bus cycles used (may need to set Cvm- Ctl[DISCE] for accurate counts) DDIDS (Event 40) Number of Dstream DIDs created IDIDS (Event 41) Number of Istream DIDs created DIDNA (Event 42) Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) LDS (Event 43) Number of load issues LMLDS (Event 44) Number of local memory load IOLDS (Event 45) Number of I/O load issues DMLDS (Event 46) Number of loads that were not prefetches and missed in the cache STS (Event 48) Number of store issues LMSTS (Event 49) Number of local memory store issues IOSTS (Event 50) Number of I/O store issues IOBDMA (Event 51) Number of IOBDMAs DTLB (Event 53) Number of dstream TLB refill, invalid, or modified ex- ceptions DTLBAD (Event 54) Number of dstream TLB address errors ITLB (Event 55) Number of istream TLB refill, invalid, or address er- ror exceptions SYNC (Event 56) Number of SYNC stall cycles (may need to set Cvm- Ctl[DISCE] for accurate counts) SYNCIOB (Event 57) Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) SYNCW (Event 58) Number of SYNCWs ERETMIS (Event 64) D/eret mispredicts (CN63XX specific) LIKMIS (Event 65) Branch likely mispredicts (CN63XX specific) HAZTR (Event 66) Hazard traps due to *MTC0 to CvmCtl, Perf counter con- trol, EntryHi, or CvmMemCtl registers (CN63XX specific) Event Name Aliases The following table shows the mapping between the PMC-independent aliases supported by Performance Monitoring Counters Interface Library (libpmc, -lpmc) and the underlying hardware events used. Alias Event instructions RET branches BR branch-mispredicts BS SEE ALSO pmc(3), pmc.atom(3), pmc.core(3), pmc.iaf(3), pmc.k7(3), pmc.k8(3), pmc.mips24k(3), pmc.p4(3), pmc.p5(3), pmc.p6(3), pmc.soft(3), pmc.tsc(3), pmc_cpuinfo(3), pmclog(3), hwpmc(4) HISTORY The pmc library first appeared in FreeBSD 6.0. AUTHORS The Performance Monitoring Counters Interface Library (libpmc, -lpmc) li- brary was written by Joseph Koshy <jkoshy@FreeBSD.org>. MIPS support was added by George Neville-Neil <gnn@FreeBSD.org>. FreeBSD 13.0 March 24, 2012 FreeBSD 13.0
NAME | LIBRARY | SYNOPSIS | DESCRIPTION | SEE ALSO | HISTORY | AUTHORS
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